To protect integrated circuits from damage due to electrostatic discharge events, electrostatic discharge power clamp circuits are used. Traditional electrostatic discharge power clamp circuits require relatively long amounts of time to reset putting the circuits being protected at risk during consecutive electrostatic discharge events. Schemes to reduce this reset time result in the trigger portion of the electrostatic discharge power clamp circuits being overly sensitive to noise causing false triggers. Accordingly, there exists a need in the art to mitigate the deficiencies and limitations described hereinabove.